A microcomputer has been proposed that performs a voltage monitoring function by using an analog to digital (A/D) converter. A microcomputer 15 shown in FIG. 9 includes a central processing unit (CPU) 1, an oscillator 2, an oscillation stop circuit 3, an oscillation control circuit 4, and a frequency divider circuit 5, a voltage detection circuit 6, and an A/D analog circuit 7. The voltage detection circuit 6 includes an A/D analog controller 8, a threshold set register 9, a detection start register 10, a result store register 11, an interrupt register 12, an interrupt enable register 13, and an AND gate 14. The microcomputer 15 monitors and detects a voltage applied to a voltage input terminal by using the voltage detection circuit 6.
When the microcomputer 15 operates in a normal mode, the CPU 1 is supplied with a clock signal from the oscillator 2 through the oscillation stop circuit 3. The clock signal passing through the oscillation stop circuit 3 is fed to the voltage detection circuit 6 through the frequency divider circuit 5. When the microcomputer 15 switches from the normal mode to a low power consumption mode (i.e., sleep mode), the CPU 1 controls the oscillation control circuit 4 to stop the oscillator 2 and the oscillation stop circuit 3.
The A/D analog circuit 7 and the A/D analog controller 8 form a successive approximation register type A/D converter, for example. When a start flag is set in the detection start register 10, the A/D analog controller 8 starts its operation. The voltage applied to the voltage input terminal is inputted to the A/D analog circuit 7. The A/D analog circuit 7 converts the inputted voltage to detection voltage data by comparing the inputted voltage with reference voltages fed from the A/D analog controller 8. The detection voltage data is outputted to the A/D analog controller 8.
The A/D analog controller 8 compares the detection voltage data with threshold voltage data, which is stored in the threshold set register 9. The result of the comparison is stored in the result store register 11 so that the voltage monitoring function is completed. When the voltage monitoring function is completed, an interrupt flag is set in the interrupt register 12. If an interrupt enable flag is set in the interrupt enable register 13 at this time, the AND gate 14 outputs an interrupt request signal to the CPU 1.
As shown in FIG. 10, after the microcomputer 15 switches to the sleep mode, the oscillator 2 stops its operation. As a result, the clock signal is not supplied to the voltage detection circuit 6 so that the voltage detection circuit 6 cannot perform its operation. Therefore, the microcomputer 15 cannot perform the voltage monitoring function in the sleep mode.
There may be a need to periodically and successively continue the voltage monitoring function, regardless of whether the microcomputer 15 operates in the normal mode or the sleep mode. In this case, the whole microcomputer 15 including the CPU 1 needs to wake up from the sleep mode to perform the voltage monitoring function. As a result, power consumption of the microcomputer 15 becomes large so that power efficiency of the microcomputer 15 becomes low.